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CEVA SGMII IP provides a low power and robust solution for connecting
external Gigabit Ethernet PHY chips to the corresponding MAC layers
embedded in a separate SoC, via the Serial GMII interface standard.
By combining the silicon-proven ultra low power CEVA Serialiser/Deserialiser
(SerDes) technology with a fully compliant SGMII protocol layer,
CEVA SGMII is an ideal solution for applications looking to integrate
SGMII ports without relying on a separate clock line to time the
data transfer and hence delivers the lowest power and pin budget
possible.
The CEVA SGMII platform is currently available on TSMC 0.18uG and
TSMC 0.13uG
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Now |
TSMC 0.18um
TSMC 0.13um
TSMC 90nm |
Now
Now
Q3 2005 |
| Other |
Contact CEVA |
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| IP Package |
- SGMII Protocol - Verilog RTL package
- SGMII PMA - GDSII hard marco
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| Dev Environment |
- PCI-X based FPGA development board for SGMII Protocol
plus daughter board containing SGMII PMA silicon.
- Test software for PC, running on Windows 2000 or later
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| Info & Resources |
CEVA
SGMII Product Note (pdf 30kb) |
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