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CEVA-TeakLite-III™ - Dual-MAC, native 32-bit DSP Architecture

CEVA-TeakLite-III™ is a third-generation DSP architecture based on the broadly adopted TeakLite family of DSP cores.

For the first time in the TeakLite DSP family, CEVA-TeakLite-III delivers native 32-bit processing and a dual Multiply-Accumulate (MAC) architecture, making the DSP ideal for deployment in High Definition (HD) audio applications requiring advanced audio standards such as Dolby Digital Plus 7.1, Dolby TrueHD and DTS-HD. Additional target applications for CEVA-TeakLite-III include low-cost 2G/2.5G/3G wireless baseband modems, wideband voice and audio processors, portable media players, voice-over-IP residential gateways and dual mode cellular/voice-over-WiFi handsets.

In addition to 32-bit processing power and a dual-MAC architecture, CEVA-TeakLite-III features a 10-stage pipeline, enabling the core to reach operating speeds of up to 425MHz in a 65nm process (worst-case conditions and process). Compared to CEVA-TeakLite, initial performance show it to be up to 4 times faster on basic operations and 2 times better on most popular audio codecs.

For next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. A FFT accelerator further boosts audio performance and reduces power consumption.

3G multimode and portable audio applications are enhanced through dual 16-bit multipliers, a built-in Viterbi accelerator and a set of SIMD and parallel instructions. By utilizing a 10-stage pipeline, the CEVA-TeakLite-III runs at 350MHz in a 90nm G process, and up to 425MHz in a 65nm G process, using the worst-case corner.

Next-generation wireless and digital media devices require larger program size, increased local frame buffers and efficient multi-tasking. CEVA-TeakLite-III expands its predecessor's addressable memory space by offering a 4 GB linear address space for code and data memory. The core also offers a 32-bit unified general purpose register bank and a 32-bit scalar unit, with arithmetic, logical, bit manipulation and quick look-up-table access capabilities, as well as a branch prediction mechanism, to further enhance its micro-controller feature set.

CEVA-TeakLite-III Webinar

Introducing CEVA-TeakLite-III
Addressing the Design Challenges of High Definition (HD) Audio and Other Consumer Applications with a 32-bit DSP Engine

Watch Webinar on-demand

CEVA-TeakLite-III Product Note

For a more in-depth look at the CEVA-TeakLite-III DSP Core, Download the CEVA-TeakLite-III Product Note (

pdf, 114kb)

CEVA-TeakLite-III Key Features

	Dual-MAC, native 32-bit architecture
	Backward compatible with CEVA- TeakLite and CEVA-TeakLite-II cores
	Combined DSP and RISC-oriented features 4GB memory space 32 bit scalar unit 32 bit register bank 64 bit memory bandwidth
	32 x 32 MAC unit to provide efficient support of advanced audio standards
	10-stage pipeline enabling high speed design
	Embedded CEVA-Quark™ 16-bit ISA enables better code density
	Multiple subsystem options to best fit customer system needs
	In-house developed SW tools

CEVA-TeakLite-III embeds the CEVA-Quark™ instruction set, a comprehensive stand-alone 16-bit ISA that allows customers to develop complete applications for cost-sensitive markets. Moreover, customers can seamlessly mix CEVA-Quark instructions with more advanced instructions without the need for mode switching. This enables better code density for CEVA-TeakLite-III based designs and requires less memory, die size and power as a result.

CEVA-TeakLite-III is fully compatible with the CEVA-TeakLite, CEVA-TeakLite-II and Oak™ DSP architectures, allowing licensees to leverage both existing applications and the large software install base already available from CEVA and the CEVAnet™ third-party development community.

CEVA-TeakLite-III is a fully synthesizable soft core and a process-independent design that allows licensees to specify the silicon area, power consumption and speed that best suits their needs.

CEVA-TeakLite-III is a family of DSP cores, each configured to target a specific application. Each core consists of a DSP engine, configurable L1/L2 memories and caches, and other system peripherals and interfaces. Using application-specific configurations ensures rapid deployment of the core and guarantees the performance in a complete system. This also enables customers to balance performance with die size in their target system-on-chip.

	CEVA-TL3210	CEVA-TL3211
L1 Data	TCM	TCM + Cache
L1 Program	TCM + Direct Map Cache	TCM + Cache
L2	Customer Dependant	TCM + 4-way Cache
MMU	No	Yes
DMAs	External	2D DMA + manager
System I/Fs	3x AHBLite, APB3	3x AHBLite / AXI, APB3

CEVA-TeakLite-III Block Diagram

The CEVA-TeakLite-III is accompanied by the advanced Integrated Development Environment (IDE) based Software Development Tools for embedded applications, supporting Windows, Linux and Solaris operating systems, including

Highly optimizing C and C++ compiler
Macro assembler and linker
Advance Graphic User Interface debugger and simulator
Tight MATLAB bi-directional connectivity
Integrated graphic application profiler
Various utilities and converters

The deliverables include complete and fully automated reference design implementation along with a verification & simulation environments. CEVA-TeakLite-III design can also be ported to an FPGA for prototyping and system integration, prior to taping out the actual silicon.

CEVA-TeakLite-III is backed up by a wide variety of software, applications and algorithms available by CEVA and the CEVAnet third party community.



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